%FILENAME%
iverilog-13.0-1.1-x86_64_v3.pkg.tar.zst

%NAME%
iverilog

%BASE%
iverilog

%VERSION%
13.0-1.1

%DESC%
Icarus Verilog compiler and simulation tool

%CSIZE%
2464922

%ISIZE%
7465152

%SHA256SUM%
c83992007fc460e8ec928d3f395a2f2d7399b0f66baaf5d1aad58d3d44893930

%PGPSIG%
iQGzBAABCgAdFiEEiC3P5I4gUdSOJWKr87YHSI2zWkcFAmmlXKAACgkQ87YHSI2zWkfG6wv+IGRZpclVJ643WQMOJrUSniCy8R6sBuXZRySnsRPj7ltvwAoH0lDbBT4LckYT/XWqGwENTGEITkBWoNscbl80QL6wzswoLMGmXVhfl94dO3mLfjOZuVVAYXBdup6IwSlT3efiaQk+foMI1zfrCBq+0tZ5e4E0o7GU88V3CVyD1gwXjuzhIb5MZwiRRaIGUfjkii2fkBufDTGYpAbOOBrlHuZbkoVebzRBdpBbxSBrSkjlaDXOpPZTUHThfyJM985xmnhl3v8jut7gU78TMsLkP12BwciWG7xXwYvaBuf4KE1HIpVs2K92O+9/vqx3+f0dvlxUQlUrmgvcjNHzorL51rPxlYmb0G6ouJZRP148w3QymjJSLvocxo3zVxzF2d1OVL62oiDXkTjpSMIdUvqw1PiXoNv90sh7IbSM/VL0RFeKjPRdAw46UsQctieDmiSBF1ximD7Vuf9n+7IVvQu/cbLoIhxKhWrNct4gT99mlnxh1HXfwdYXOO2CTaucxLRC

%URL%
https://github.com/steveicarus/iverilog

%LICENSE%
GPL

%ARCH%
x86_64_v3

%BUILDDATE%
1772444788

%PACKAGER%
CachyOS <admin@cachyos.org>

%DEPENDS%
bzip2
zlib

%MAKEDEPENDS%
git
gperf

